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Synplify pro component name how to#

However, we shall see later in this article that the Lattice device can pack wider shift registers into block RAM. The Lattice iCE40 FPGA, which I used in this example, doesn’t have an alternative option for packing 1-bit shift register, so it’s implemented entirely in 128 FFs. Intel uses a technology that they call ALTSHIFT_TAPS for implementing RAM-based shift registers. In the Intel FPGA, adaptive logic modules (ALMs) and one block RAM (BRAM) is used instead of flip-flops. Lookup tables (LUTs) used in such a way are counted as “LUTRAM” in the Vivado resource usage report. Instead of using expensive FFs, the synthesis tools have used special built-in features of the logic blocks.

Intel Quartus II (Cyclone V): 11 ALMs + 1 BRAMĮven though the shift register should require 128 flip-flops (FFs), we see that the resource usage reported by Vivado and Quartus is far less.

Xilinx Vivado (Zynq): 4 LUTs (LUTRAM) + 2 FFs.

These are the resources consumed for Xilinx, Intel (Altera), and Lattice FPGAs with the sr_depth generic set to 128. The three implementations that follow will synthesize into the same logic. To keep it simple, we’re going to use the same entity for multiple architectures, even though the rst and enable inputs are unused by some of them. We will use the entity declaration shown below for all of the following examples involving one-bit shift registers. The depth is configurable through a generic constant. The input and output of this shift register is a single bit, a std_logic value. Let’s first have a look at different methods of creating a one-bit shift register. The 1-bit shift register with generic depth You can improve performance in magnitudes by being mindful of how you write your VHDL code. Many FPGAs have logic elements that can double as specialized shift register primitives. While any shift register is suitable for creating generic, smaller buffers, there are methods of efficiently creating larger ones.

Synplify pro component name how to#

Read about how to create a ring buffer FIFO in block RAM to learn about such a solution that’s not a shift register. This article will only consider the shift register, even though there exist data structures that use fewer resources for larger FIFOs. To understand the basics of the shift register, I recommend viewing the VHDL tutorial about the std_logic_vector.

Every time a new element enters the queue, it shifts the existing ones one place further away from the input. You can dramatically reduce the number of consumed resources by choosing the right shift register implementation for your needs and FPGA architecture.Ī shift register implements a FIFO of fixed length. There are many ways to create a shift register in VHDL, though not all of them are equal.